Pinned photodiode photodetector with common pixel transistors and binning capability

ABSTRACT

A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight.A CMOS active pixel image sensor includes a plurality of pinned photodiode photodetectors that use a common output transistor. In one configuration, the charge from two or more pinned photodiodes may be binned together and applied to the gate of an output transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

This applicationNotice: More than one reissue application has been filedfor the reissue of U.S. Pat. No. 6,794,214. The reissue applications areapplication Ser. No. 12/413,626 (the present application), which is adivisional reissue application of reissue application Ser. No.11/524,495, which is a reissue of U.S. Pat. No. 6,794,214, issued onSep. 21, 2004. U.S. Pat. No. 6,794,214 is a continuation of U.S. patentapplication Ser. No. 09/378,565, filed Aug. 19, 1999 now U.S. Pat. No.6,239,456, which claims the benefit of the U.S. Provisional ApplicationNo. 60/097,135, filed on Aug. 19, 1998, which is incorporated herein byreference.

BACKGROUND

Certain applications require measuring aspects that are based on thespeed of light.

For example, range finding can be carried out using optics. An opticalsignal is sent. The reflection therefrom is received. The time that ittakes to receive the reflection of the optical signal gives anindication of the distance.

The so called lock-in technique uses an encoded temporal pattern as asignal reference. The device locks into the received signal to find thetime of receipt. However, noise can mask the temporal pattern.

A lock in photodetector based on charged coupled devices or CCDs hasbeen described in Miagawa and Kanada “CCD based range finding sensor”IEEE Transactions on Electronic Devices, volume 44 pages 1648-1652 1997.

CCDs are well known to have relatively large power consumption.

SUMMARY

The present application describes a special kind of lock in detectorformed using CMOS technology. More specifically, a lock in detector isformed from a pinned photodiode. The photodiode is modified to enablefaster operation.

It is advantageous to obtain as much readout as possible to maximize thesignal to noise ratio. The pinned photodiode provides virtually completecharge transfer readout.

Fast separation of the photo-generated carriers is obtained byseparating the diode into smaller sub-parts and summing the outputvalues of the subparts to obtain an increased composite signal.

BRIEF DESCRIPTION OF THE DRAWINGS

These an other aspects will now be described in detail with reference tothe accompanying drawings, wherein:

FIG. 1 shows a basic block diagram of the system;

FIG. 2 shows a block diagram of the multiple photodiode parts;

FIG. 3 shows a block diagram of the system as used in range finding;

FIG. 4a and 4b show pixel layouts; and

FIG. 5 shows a cross section of the pinned photodiode.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present application uses a special, multiple output port pinnedphotodiode as the lock in pixel element. The photodiode is preferablypart of a CMOS active pixel image sensor, of the type described in U.S.Pat. No. 5,471,505. Hence, the system preferably includes in-pixelbuffer transistors and selection transistors, in addition to the CMOSphotodetector.

FIG. 1 shows a pinned photodiode with four output ports, labeled asout1-out4. Each of the output ports is used to receive a reflection fora specified time duration. Each output becomes a “bin”. The counting ofthe amount of information in the bins enables determination of thereflection time, and hence the range.

Pinned photodiodes are well known in the art and described in U.S. Pat.No. 5,904,493. A pinned photodiode is also known as a hole accumulationdiode or HAD, or a virtual phase diode or VP diode. Advantages of thesedevices are well known in the art. They have small dark current due tosuppression of surface generation. They have good quantum efficiencysince there are few or no polysilicon gates over the photosensitiveregion. Pinned photodiodes can also be made into smaller pixels becausethey have fewer gates.

The basic structure of the pinned photodiode lock in pixel is shown inFIG. 1. Four switched integrators are formed respectively at four outputports. Each gate is enabled during a specified period. The differentintegrators integrate carriers accumulated during the different periods.The first integrator accumulates carriers between 0 and π/2, the secondbetween π/2 and π, the third between π and 3π/2 and the fourth between3π/2 and 2πtime slots.

Assuming the light to be a cosine phase, then the phase shift of thedetected light is given byarctan[(L1-L3)/(L2-L4)],where L1, L2, L3 and L4 are the amplititudes of the samples from therespective first, second, third and fourth integrators. These fourphases are obtained from the four outputs of the photodiode.

The first pinned photodiode 100 is connected to an output drain 102 viagate 1, element 104. This receives the charge for the first bin.Similarly, gates 2, 3 and 4 are turned on to integrate/bin from thesecond, third and fourth periods.

It is important to obtain as much signal as possible from thephotodiode. This can be done by using a large photodiode. However, itcan take the electrons a relatively long time to escape from a largephotodetector.

The present system divides the one larger photodiode into a number ofsmaller diodes, each with multiple output ports. FIG. 2 shows thesystem.

A number of subpixels are formed. Each includes a number of pinnedphotodiodes 200, each with four ports. Each of the corresponding portsare connected together in a way that allows summing the outputs of thephotodiodes. For example, all the gate 1 control lines are connectedtogether as shown. The outputs from all the port 1s are also summed, andoutput as a simple composite output. Similarly, ports 2, 3 and 4's areall summed.

FIG. 3 shows the circuit and driving waveforms for the system when usedas a range finder. A pulse generator drives selection of the activeoutput. Each time period is separately accumulated, and output. If a 40MHZ pulse generator is used, 25 ns resolution can be obtained.

FIGS. 4A and 4B show representative pixel layouts. FIG. 4A shows a 6 by6 square micron pixel layout while FIG. 4B shows an 8½ by 8½ micronpixel layout. In both Figures, four outputs are shown.

FIG. 5 shows a cross sectional potential diagram of an exemplary pinnedphotodiode.

Assuming the operation frequency of modulated light is 10 megahertz witha 25 nanosecond integration slot, the generator carrier has a time offlight within this limit. This resolution time constrains the size ofthe detector. In addition, the characteristic diffusion time in asemiconductor device is L²/D, where D is the diffusion coefficient. Thistime originates from the continuity equation and the diffusion equation,and defines how soon the steady state will be established in the area ofsize L. Hence, for a 10 cm square per second electron diffusioncoefficient, the characteristic size of the pinned photodiode could beless than 5 microns.

Other embodiments are also contemplated to exist within this disclosure.For example, other numbers of output ports, e.g. 2-8, are possible.While this application describes using a pinned photodiode, similaroperations could be carried out with other CMOS photodetectors, e.g.,photodiodes and photogates.

Such modifications are intended to be encompassed within the followingclaims.

1. A method, comprising: accumulating photocarriers in each of aplurality of photocarrier integrators and successively enabling each ofsaid plurality of photocarrier integrators to connect to a commonphotodiode, each of said photocarrier integrators connecting to saidcommon photodiode through a respective photodiode output port, saidplurality of photocarrier integrators accumulating photocarriersgenerated by said photodiode during different time periods from oneanother.
 2. A method as in claim 1, wherein said enabling comprisesactuating a gate that is connected between each said photocarrierintegrator and said photodiode.
 3. A method as in claim 2, furthercomprising, after said enabling, detecting a number of carriersaccumulated in said photodiode during at least two of said time periodsby detecting the number of photocarriers accumulated in at least twosaid photocarrier integrators.
 4. A method as an claim 2, wherein saidphotodiode is a pinned photodiode, and further comprising, after saidenabling, detecting a number of carriers accumulated in said pinnedphotodiode during at least two of said time periods by decting thenumber of photocarriers accumulated in at least two said photocarrierintegrators.
 5. A method as in claim 1, wherein there are four of saidphotocarrier integrators, and said successively enabling comprises usinga first photocarrier integrator to accumulate photocarrier between times0 and π/2, a second photocarrier integrator to accumulate photocarriersbetween times π/2 and π; a third photocarrier integrator to accumulatephotocarriers between times π and 3π/2, and a fourth photocarrierintegrator to accumulate photocarriers between times 3π/2 and 2π.
 6. Amethod as in claim 1, further comprising detecting a phase shift oflight received by said photodiode by detecting accumulated charge in atleast two photocarrier integrators.
 7. A method, comprising: generatingphotocarriers in a photodiode within a pixel during a plurality of timeperiods; accumulating photocarriers in each of a plurality ofphotocarrier integrators within said pixel such that each photocarrierintegrator accumulates photocarriers generated during a time perioddifferent from a time period in which other photocarrier integratorsaccumulate photocarriers; and sampling said photocarriers from saidphotocarrier integrators; determining a range of an object using saidsampled photocarriers.
 8. A method as in claim 7, further comprisingcontrolling each of said photocarrier integrators to be connected tosaid photodiode during said different time period.
 9. A method as inclaim 8, wherein said controlling comprises enabling a gate, said gatebeing connected to said photodiode and to one of said photocarrierintegrators.
 10. A method as in claim 9, wherein there are four of saidphotocarrier integrators, and wherein said enabling comprisessuccessively enabling a first photocarrier integrator to accumulatephotocarriers between times 0 and π/2, a second photocarrier integratorto accumulate photocarriers between times π/2 and π; a thirdphotocarrier integrator to accumulate photocarriers between times π and3π/2, and a fourth photocarrier integrator to accumulate photocarriersbetween times 3π/2 and 2π.
 11. A method as in claim 7, wherein there arefour of said photocarriers integrators, and said sampling comprisessampling photo carriers which are 90 degrees out of phase with oneanother.
 12. A method, comprising: sampling a plurality of differentsamples of light in a photodiode, each of said plurality of differentsamples being 90 degrees out of phase with one another; and successivelygating photocarriers representing each of said different samples fromsaid photodiode through a respective output port, each output portassociated with a respective photocarrier integrator, such that eachphotocarrier integrator accumulates a different sample than other ofsaid photocarrier integrators.
 13. A method as in claim 12, furthercomprising detecting a phase shift using said samples of light.
 14. Amethod as in claim 12, wherein there are four different gates connectedto said photodiode each gating a different sample.
 15. A method as inclaim 12, wherein there are four photocarrier integrators, and whereinsaid act of gating comprises successively enabling a first photocarrierintegrator to accumulate photocarriers between times 0 and π/2, a secondphotocarrier integrator to accumulate photocarriers between times π/2and π; a third photocarrier integrator to accumulate photocarriersbetween times π and 3π/2, and a fourth photocarrier integrator toaccumulate photocarriers between times 3π/2 and 2π.
 16. A method ofoperating a range finding sensor, the method comprising; providing aplurality of photodiodes, each photodiode having a first output port forswitchably coupling each respective photodiode to a first photocarrierintegrator in a same pixel as said photodiode and a second output portfor switchably coupling each photodiode to a second photocarrierintegrator in a same pixel as said photodiode; generating firstphotocarriers in said photodiodes in response to light received during afirst time period; transferring said first photocarriers to respectivefirst photocarrier integrators via said first output ports; generatingsecond photocarriers in said photodiodes in response to light receivedduring a second time period; and transferring said second photocarriersto respective second photocarrier integrators via said second outputports.
 17. The method of claim 16, further comprising outputting saidfirst photocarriers from first photocarrier integrators and outputtingsaid second photocarriers from second photocarrier integrators.
 18. Themethod of claim 17, wherein the act of outputting said firstphotocarriers comprises summing outputs of all of said firstphotocarrier integrators, and wherein the act of outputting said secondphotocarriers comprises summing outputs of all of said secondphotocarrier integrators.
 19. The method of claim 16, further comprisingcounting the amount of photocarriers in said first photocarriersintegrator and counting the amount of said second photocarriers in saidsecond photocarrier integrator.
 20. The method of claim 19, furthercomprising determining a range of an object using the results of saidacts of counting.
 21. The method of claim 16, wherein said act ofproviding a plurality of photodiodes includes providing said pluralityof photodiodes within a common pixel.
 22. The method of claim 16,wherein said act of transferring said first photocarriers comprisestransferring said first photocarriers to respective first output drainsby operating first gates connected to said photodiodes and said firstoutput drains, and wherein said act of transferring said secondphotocarriers comprises transferring said second photocarriers torespective second output drains by operating second gates connected tosaid photodiodes and said second output drains.
 23. The method of claim16, wherein each photodiode further has a third output port forswitchably coupling each photodiode to a third photocarrier integratorin a same pixel as said photodiode and a fourth output port forswitchably coupling each photodiode to a fourth photocarrier integratorin a same pixel as said photodiode, and further comprising: generatingthird photocarriers in said photodiodes in response to light receivedduring a third time period; transferring said third photocarriers torespective third photocarrier integrators via said third output ports;generating fourth photocarriers in said photodiodes in response to lightreceived during a fourth time period; and transferring said fourthphotocarriers to respective fourth photocarrier integrators via saidfourth output ports.
 24. The method of claim 23, further comprisingoutputting said first photocarriers from said first photocarrierintegrators, outputting said second photocarriers from said secondphotocarrier integrators, outputting said third photocarriers from saidthird photocarrier integrators, and outputting said fourth photocarriersfrom said fourth photocarrier integrators.
 25. The method of claim 24,wherein the act of outputting said first photocarriers comprises summingoutputs of all of said first photocarrier integrators, wherein the actof outputting said second photocarriers comprises summing outputs of allof said second photocarrier integrators, wherein the act of outputtingsaid third photocarriers comprises summing outputs of all of said thirdphotocarrier integrators, and wherein the act of outputting said fourthphotocarriers comprises summing outputs of all of said fourthphotocarrier integrators.
 26. A method comprising: providing an array ofpixels of a CMOS active pixel image sensor, the array comprising aplurality of rows of pinned photodiodes and a plurality of columns ofpinned photodiodes, and including first, second, third, and fourthpinned photodiodes in first, second, third, and fourth different rows,respectively, of the plurality of rows; providing an in-pixel buffertransistor comprising a gate and coupled between a supply voltage and anoutput node, wherein the buffer transistor is configured to control atransfer of charge between the supply voltage and the output node inaccordance with a voltage applied to the gate; providing a firsttransfer transistor coupled between the first pinned photodiode and thegate, wherein the first transfer transistor is configured to control atransfer of charge between the first pinned photodiode and the gate;providing a second transfer transistor coupled between the second pinnedphotodiode and the gate, wherein the second transfer transistor isconfigured to control a transfer of charge between the second pinnedphotodiode and the gate; providing a third transfer transistor coupledbetween a third pinned photodiode and the gate, wherein the thirdtransfer transistor is configured to control a transfer of chargebetween the third pinned photodiode and the gate; providing a fourthtransfer transistor coupled between a fourth pinned photodiode and thegate, wherein the fourth transfer transistor is configured to control atransfer of charge between the fourth pinned photodiode and the gate;and providing a reset transistor coupled to the gate, wherein when thereset transistor is enabled, charge is transferred to the gate.
 27. Themethod of claim 26, further comprising enabling the first transfertransistor and the second transfer transistor during a same period oftime to bin charge from both the first pinned photodiode and the secondpinned photodiode on the gate.
 28. The method of claim 26, furthercomprising enabling the first, second, third, and fourth transfertransistors during a same period of time to bin charge from the first,second, third and fourth pinned photodiodes on the gate.
 29. The methodof claim 26, further comprising providing an in-pixel selectiontransistor.
 30. The method of claim 26, wherein the reset transistor iscoupled between the gate and the supply voltage.
 31. The method of claim26, further comprising: providing a first charge collection region in asemiconductor material adjacent to the first and second pinnedphotodiodes, wherein the first transfer transistor is configured tocontrol a transfer of charge between the first pinned photodiode and thefirst charge collection region and the second transfer transistor isconfigured to control a transfer of charge between the second pinnedphotodiode and the first charge collection region; providing a secondcharge collection region in the semiconductor material adjacent to thethird and fourth pinned photodiodes, wherein the third transfertransistor is configured to control a transfer of charge between thethird pinned photodiode and the second charge collection region and thefourth transfer transistor is configured to control a transfer of chargebetween the fourth pinned photodiode and the second charge collectionregion; and providing an electrical interconnect above the semiconductormaterial to couple the first region and the second region to the gate.32. The method of claim 26, wherein the first, second, third, and fourthpinned photodiodes are in a same column of the plurality of columns ofpinned photodiodes.
 33. A method comprising: accumulating charge in afirst pinned photodiode of a first pixel that occupies a first row of anarray of pixels of a CMOS active pixel imager comprising in-pixel buffertransistors; transferring charge from the first pinned photodiodedirectly to a first diffusion region via a first transistor;accumulating charge in a second pinned photodiode of a second pixel thatoccupies a second row, below the first row, of the array; transferringcharge from the second pinned photodiode directly to the first diffusionregion via a second transistor; accumulating charge in a third pinnedphotodiode of a third pixel that occupies a third row, below the secondrow, of the array; transferring charge from the third pinned photodiodedirectly to a second diffusion region, separate from the first diffusionregion, via a third transistor; accumulating charge in a fourth pinnedphotodiode of a fourth pixel that occupies a fourth row, below the thirdrow, of the array; transferring charge from the fourth pinned photodiodedirectly to the second diffusion region via a fourth transistor;applying charge from the first diffusion region to a gate of a fifthtransistor coupled between a supply voltage and an output; and applyingcharge from the second diffusion region to the gate of the fifthtransistor, wherein the fifth transistor is common to the first, second,third, and fourth pixels.
 34. The method of claim 33, further comprisingturning on the first transistor and the second transistor during a sameperiod of time.
 35. The method of claim 34, further comprising turningon the third transistor and the fourth transistor during a same periodof time.
 36. The method of claim 33, further comprising resetting thefirst and second diffusion regions via a single reset transistor. 37.The method of claim 36, wherein the CMOS active pixel image sensorfurther comprises in-pixel selection transistors.
 38. The method ofclaim 33, wherein the CMOS active pixel image sensor further comprisesin-pixel selection transistors.
 39. The method of claim 33, wherein thefirst, second, third, and fourth pixels occupy a single column of thearray.
 40. A method comprising: enabling a CMOS active pixel imagesensor to be exposed to light, wherein first, second, third, and fourthpinned photodiodes disposed in first, second, third, and fourth adjacentrows of photodiodes, respectively, of the CMOS active pixel image sensorare configured to generate first, second, third, and fourth charges uponexposure to the light, respectively; enabling the first charge to betransferred to a gate of an output transistor via a first transfertransistor between the first pinned photodiode and the gate; enablingthe second charge to be transferred to the gate via a second transfertransistor between the second pinned photodiode and the gate; enablingthe third charge to be transferred to the gate via a third transfertransistor between the third pinned photodiode and the gate; andenabling the fourth charge to be transferred to the gate via a fourthtransfer transistor between the fourth pinned photodiode and the gate.41. The method of claim 40, wherein the enabling the first charge to betransferred and the enabling the second charge to be transferred occurduring a same period of time.
 42. The method of claim 40, wherein theenabling the first charge to be transferred, the enabling the secondcharge to be transferred, the enabling the third charge to betransferred, and the enabling the fourth charge to be transferred occurduring a same period of time.
 43. The method of claim 40, furthercomprising enabling the gate to be reset via a reset transistor.
 44. Themethod of claim 40, further comprising enabling pixels of the CMOSactive pixel image sensor to be buffered using in-pixel buffertransistors.
 45. The method of claim 44, further comprising enablingpixels of the CMOS active pixel image sensor to be selected for readoutusing in-pixel selection transistors.
 46. The method of claim 44,wherein the first and second transfer transistors share a common firstsource/drain region adjacent to gates of the first and second transfertransistors, the third and fourth transfer transistors share a commonsecond source/drain region adjacent to gates of the third and fourthtransfer transistors, and the common first source/drain region iscoupled to the common second source/drain region via an electricalinterconnect disposed above the first and second source/drain regions.47. The method of claim 40, wherein the first, second, third, and fourthpinned photodiodes are disposed in a first column of photodiodes.
 48. Amethod comprising: providing a device containing a CMOS active pixelimage sensor, the sensor comprising an array of pixels and a pluralityof pinned photodiodes arranged in rows including at least first, second,third, and fourth separate rows of photodiodes, each pixel including atleast one pinned photodiode, the device configured to expose the CMOSactive pixel image sensor to light, in response to which each pinnedphotodiode of the plurality of pinned photodiodes is to generate charge;providing a first circuit configured to operate a gate of a firstn-channel transfer transistor coupled between a first pinned photodiodeof the first row of the plurality of pinned photodiodes and a gate of ann-channel in-pixel buffer transistor, wherein the buffer transistor iscoupled between a supply voltage and an output; providing a secondcircuit configured to operate a gate of a second n-channel transfertransistor coupled between a second pinned photodiode of the second rowof the plurality of pinned photodiodes and the gate of the buffertransistor; providing a third circuit configured to operate a gate of athird n-channel transfer transistor coupled between a third pinnedphotodiode of the third row of the plurality of pinned photodiodes andthe gate of the buffer transistor; providing a fourth circuit configuredto operate a gate of a fourth n-channel transfer transistor coupledbetween a fourth pinned photodiode of the fourth row of the plurality ofpinned photodiodes and the gate of the buffer transistor; and providinga fifth circuit configured to operate a gate of an n-channel resettransistor coupled to the gate of the buffer transistor to reset avoltage on the gate of the buffer transistor.
 49. The method of claim48, wherein the first circuit and the second circuit are configured tooperate the first transfer transistor and the second transfertransistor, respectively, in a manner that causes charge from the firstpinned photodiode and the second pinned photodiode to be binned togetheron the gate of the buffer transistor.
 50. The method of claim 48,wherein the first, second, third, and fourth circuits are configured tooperate the first, second, third, and fourth transfer transistors,respectively, in a manner that causes charge from the first, second,third, and fourth pinned photodiodes to be binned together on the gateof the buffer transistor.
 51. The method of claim 48, further comprisingproviding a plurality of in-pixel selection transistors.
 52. The methodof claim 48, wherein each pixel includes at least one buffer transistor.53. The method of claim 48, wherein the reset transistor is coupledbetween the gate of the buffer transistor and the supply voltage. 54.The method of claim 48, further comprising: providing a first chargecollection region in a semiconductor material adjacent to the first andsecond pinned photodiodes, wherein the first transfer transistor isconfigured to control a transfer of charge between the first pinnedphotodiode and the first charge collection region and the secondtransfer transistor is configured to control a transfer of chargebetween the second pinned photodiode and the first charge collectionregion; and providing a second charge collection region, separate fromthe first region, in the semiconductor material adjacent to the thirdand fourth pinned photodiodes, wherein the third transfer transistor isconfigured to control a transfer of charge between the third pinnedphotodiode and the second charge collection region and the fourthtransfer transistor is configured to control a transfer of chargebetween the fourth pinned photodiode and the second charge collectionregion.
 55. The method of claim 54, wherein the first charge collectionregion is a drain of both the first and second transfer transistors, andthe second charge collection region is a drain of both the third andfourth transfer transistors.
 56. The method of claim 55, furthercomprising providing an electrical interconnect above the semiconductormaterial to couple the first region and the second region to the gate.57. The method of claim 48, wherein the first, second, third, and fourthpinned photodiodes are arranged in a single column of the plurality ofpinned photodiodes.
 58. A method comprising: exposing a CMOS activepixel imager to light; generating signals responsive to the light in anarray of pixels of the imager using photodiodes and in-pixel buffertransistors, comprising the steps of: activating a first transfertransistor to transfer charge from a first photodiode in a first row ofthe array to a gate of an in-pixel buffer transistor of the imagesensor; activating a second transfer transistor to transfer charge froma second photodiode in a second row of the array to the gate; activatinga third transfer transistor to transfer charge from a third photodiodein a third row of the array to the gate; and activating a fourthtransfer transistor to transfer charge from a fourth photodiode in afourth row of the array to the gate.
 59. The method of claim 58, whereinat least two of the steps of activating occur at a same time.
 60. Themethod of claim 58, further comprising activating a reset transistor toreset the gate.
 61. The method of claim 60, further comprisingactivating an in-pixel selection transistor to selectively read anoutput from the in-pixel buffer transistor.
 62. The method of claim 61,wherein the activating the first and second transfer transistorstransfers charge to a common drain of the first and second transfertransistors, and the activating the third and fourth transfertransistors transfers charge to a common drain of the third and fourthtransfer transistors.
 63. The method of claim 58, wherein the activatingthe first and second transfer transistors transfers charge to a commondrain of the first and second transfer transistors, and the activatingthe third and fourth transfer transistors transfers charge to a commondrain of the third and fourth transfer transistors.
 64. The method ofclaim 63, wherein the first, second, third, and fourth photodiodes aredisposed in the same column of the array.
 65. The method of claim 58,wherein the first, second, third, and fourth photodiodes are disposed inthe same column of the array.